• DocumentCode
    3615095
  • Title

    Breaking the synchronous barrier for systems-on-chip communication and synchronisation [Tutorial]

  • Author

    L. Lavagno;S. Moore

  • Author_Institution
    Cadence Berkeley Labs
  • Volume
    1
  • fYear
    2004
  • fDate
    6/26/1905 12:00:00 AM
  • Keywords
    "Tutorial","Design for testability","Costs","Design engineering","Synchronization","Knowledge engineering","Integrated circuit testing","Formal verification","Design automation","Test equipment"
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-2085-5
  • Type

    conf

  • DOI
    10.1109/DATE.2004.1268805
  • Filename
    1268805
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3615095