3615095

Breaking the synchronous barrier for systems-on-chip communication and synchronisation [Tutorial]

L. Lavagno;S. Moore

Cadence Berkeley Labs

1

2004

6/26/1905 12:00:00 AM

"Tutorial","Design for testability","Costs","Design engineering","Synchronization","Knowledge engineering","Integrated circuit testing","Formal verification","Design automation","Test equipment"

ieee

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

1530-1591

0-7695-2085-5

conf

10.1109/DATE.2004.1268805

1268805