Modelling of the sigma-delta analogue to digital converters with application of VHDL-AMS

The aim of This work is to introduce the new approach of modelling, simulation and design of the sigma-delta converters using VHDL-AMS language. The two main structures of the analogue to digital converters are presented. First solution refers to the description of the 8-bit sigma-delta converter in VHDL-AMS language. On the basis of such approach the advantages and disadvantages are discussed. The second solution refers to modelling 12-bit sigma-delta converter, which is finally designed with application of CAD CADENCE environment. On the basis of this research two most promising solution are chosen and implemented in a test chip. First is the serial integrators connection (from 1/sup st/ to 4/sup th/ order) sigma-delta modulator. The second solution is based on triple first order cascade (TFOC). The design flow consists of two basic steps. In the first one, VHDL-AMS models of A/D converters are designed and simulated. Two of them are chosen and implemented into CAD CADENCE software, and verified by DRC, ERC, and LVS tests, and also post layouts simulations. In This work the simulation results of 8-bit and 12-bit sigma delta analogue to digital converters are presented. A discussion of the advantages and disadvantages of such approach is also presented.