Design for verification testability

A procedure for designing combinational circuits suitable for built-in verification testing is presented. Unlike the traditional approach, where the design of a test pattern generator follows the functional logic synthesis, in the author´s method the built-in self-test synthesis tightly interacts with the functional logic design. The experimental results indicate that a significant reduction in testing time at a negligible area/performance penalty can be obtained in the circuits designed using the proposed verification testing oriented logic synthesis procedure.