• DocumentCode
    3617674
  • Title

    Energy-delay optimization of thin-body MOSFETs for the sub-15 nm regime

  • Author

    S. Balasubramanian;J.L. Garrett;V. Vidya;B. Nikolic;T.-J. King

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    2004
  • fDate
    6/26/1905 12:00:00 AM
  • Firstpage
    27
  • Lastpage
    29
  • Abstract
    This work presents the design of enhancement-mode and accumulation-mode thin-body MOSFETs optimized in terms of energy vs. delay (E-D), and assesses the effectiveness of back-gate biasing to adjust the leakage current. It is shown that back-gated FETs (BG-FETs) can provide power savings over double-gate FETs. Since BG-FETs span a wide range in E-D space, they can provide a single-device solution for high-performance and low-power applications through adaptive supply-voltage and threshold-voltage biasing.
  • Keywords
    "MOSFETs","Double-gate FETs","CMOS technology","Design optimization","Doping","Solid modeling","Leakage current","Space technology","Delay","Programmable control"
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2004. Proceedings. 2004 IEEE International
  • Print_ISBN
    0-7803-8497-0
  • Type

    conf

  • DOI
    10.1109/SOI.2004.1391540
  • Filename
    1391540
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3617674