Level-1 silicon vertex detector trigger at Belle

We present a newly developed fast trigger system that uses the silicon vertex detector (SVD) for the Belle experiment at the KEKB energy-asymmetric e/sup +/e/sup -/ collider. It is designed to issue the trigger with a latency of 1.85 /spl mu/s for the Belle central trigger system (GDL). The primary purpose of the SVD trigger is to reduce beam-induced background events by requiring tracks that come from the interaction point. The system receives trigger signals from VA1TA front-end integrated circuits, which read out signals on the silicon-strips. SVD tracks are constructed with them in combination with the trigger information of the central drift chamber (CDC), which is located outside the SVD. Performance of the SVD trigger is evaluated with collision data.