DocumentCode :
3619074
Title :
Algorithm/architecture co-design of the generalized sampling theorem based de-interlacer [video signal processing]
Author :
A. Beric;G. de Haan;R. Sethuraman;J. van Meerbergen
Author_Institution :
Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
fYear :
2005
fDate :
6/27/1905 12:00:00 AM
Firstpage :
2943
Abstract :
De-interlacing is a major determinant of image quality in a modern display processing chain. The de-interlacing method, based on the generalized sampling theorem (GST) applied to motion estimation and motion compensation, provides the best de-interlacing results. With HDTV interlaced input material (1920*1080i), this method requires about 1000 GOPs and a communication bandwidth around 10 Gbytes/sec. We analyze and simplify the algorithm and propose a processing architecture. As a result, the operation count of the motion estimator decreases by a factor of 5.5 and the bandwidth to local pixel storage by a factor of 3.3 with only mild and acceptable quality loss. We present a task breakup and a suitable heterogeneous multi-processor architecture. The task break-up is such that the computational load of the processors is balanced and the flexibility of the architecture is preserved within the application domain. To cope with the large memory bandwidth requirements, we exploit locality of reference with multi-level scratchpad memories.
Keywords :
"Signal processing algorithms","Signal sampling","Video signal processing","Bandwidth","Image sampling","Motion estimation","Computer architecture","Image quality","Displays","Motion compensation"
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
Type :
conf
DOI :
10.1109/ISCAS.2005.1465244
Filename :
1465244
Link To Document :
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