DocumentCode :
3619265
Title :
VERILAT: verification using logic augmentation and transformations
Author :
D. Paul;M. Chattejee;D.K. Pradhan
Volume :
2
fYear :
2003
fDate :
6/25/1905 12:00:00 AM
Firstpage :
366
Lastpage :
376
Keywords :
"Circuit synthesis","Design automation","Circuit testing","DH-HEMTs","Acceleration","Logic circuits","Logic testing","Logic functions","Data structures","Boolean functions"
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003. The IEEE International Symposium on
Print_ISBN :
0-7803-7991-8
Type :
conf
DOI :
10.1109/TUTCAS.2003.1490928
Filename :
1490928
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3619265
