DocumentCode
3619745
Title
Low noise CMOS mixers
Author
C.M. Pavaluta;C.M. Neacsu;B. Dimitriu;C. Ionascu
Author_Institution
Fac. of Electron. & Telecommun., Iasi Tech. Univ. "Gh. Asachi", Romania
Volume
2
fYear
2005
fDate
6/27/1905 12:00:00 AM
Firstpage
685
Abstract
This paper presents two new mixer circuits, designed by implementing the noise cancellation technique (NCT) (Bruccoleri et al., 2001) for a CMOS transistor (MOST) on single balanced mixer architecture. The single side band (SSB) noise figure performance of the proposed down conversion mixer architectures can be as low as 3.6dB@280MHz IF, if coils are used. The conversion gain of such NCT mixer is higher than 7dB, the IP3 is -5dBm and its power consumption is smaller than 13mW at 1.8V voltage supply.
Keywords
"Noise cancellation","Circuit noise","Noise reduction","Transconductors","Noise figure","Noise generators","Transconductance","Immune system","Band pass filters","Architecture"
Publisher
ieee
Conference_Titel
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on
Print_ISBN
0-7803-9029-6
Type
conf
DOI
10.1109/ISSCS.2005.1511333
Filename
1511333
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