DocumentCode
3619881
Title
Architectural considerations for energy efficiency
Author
H.Q. Dao;B.R. Zeydel;V.O. Oklobdzija
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
fYear
2005
fDate
6/27/1905 12:00:00 AM
Firstpage
13
Lastpage
16
Abstract
The formal analysis of parallelism and pipelining is performed on an 8-bit add-compare-select element of a Viterbi decoder. The results are quantified through a study of the delay and energy behaviors of gates and complex circuits due to supply scaling and circuit optimization on a modified test setup accounting for routing cost. The energy-throughput relationships of both pipelining and parallelism are characterized in connection to their corresponding depth and degree, showing clear advantages of pipelining over parallelism.
Keywords
"Energy efficiency","Pipeline processing","Circuit testing","Performance analysis","Viterbi algorithm","Decoding","Delay","Circuit optimization","Routing","Cost function"
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN
0-7695-2451-6
Type
conf
DOI
10.1109/ICCD.2005.26
Filename
1524123
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