DocumentCode :
3620957
Title :
Optimization of Negative Gate Networks Realized in Weinberger-Likf Layout in a Boolean Level Silicon Compiler
Author :
A. Wieclawski;M. Perkowski
Author_Institution :
Warsaw Technical University, Institute of Electron Technology, Warsaw, Nowowiejska, Poland
fYear :
1984
fDate :
6/6/1905 12:00:00 AM
Firstpage :
703
Lastpage :
704
Keywords :
"Intelligent networks","Optimizing compilers","Silicon compiler","Logic","Circuits","Boolean functions","Design automation","Delay","Hardware","Cost function"
Publisher :
ieee
Conference_Titel :
Design Automation, 1984. 21st Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0542-1
Type :
conf
DOI :
10.1109/DAC.1984.1585888
Filename :
1585888
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3620957
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