Effects of using a pin-to-pin delay model on a library-free transistor/gate sizing scheme

This paper demonstrates the advantages in using a pin-to-pin delay model during the optimization of circuit performance. It is well known that pin-to-pin delay models are more accurate than a single pair of delays for gate level delay estimation, especially when complex gates are considered. For the transistor sizing problem, a pin-to-pin delay model can be used to size only the series-connected transistors passing by the gate input that belongs to the critical path. Experimental results show that performance is optimized with smaller transistor area overhead when only the critical transistors are sized instead of the whole pull-down or pull-up structure. Selective sizing approach achieved an average area gain of 1.5 for circuits containing only simple gates. For complex gate circuits the area gain ranges from 1.5 to 8.8. A fully automated library-free layout generator was used to evaluate the impact of the sizing approaches at layout level