DocumentCode
3621022
Title
Design Methodologies and CAD Tool Flows for Networks on Chips
Author
S. Murali
Author_Institution
Stanford University, smurali@stanford.edu
fYear
2005
fDate
6/27/1905 12:00:00 AM
Firstpage
1
Lastpage
1
Keywords
"Design methodology","Design automation","Network-on-a-chip","Traffic control","Process design","Telecommunication traffic","Algorithm design and analysis","Routing","Very large scale integration","Bandwidth"
Publisher
ieee
Conference_Titel
System-on-Chip, 2005. Proceedings. 2005 International Symposium on
Print_ISBN
0-7803-9294-9
Type
conf
DOI
10.1109/ISSOC.2005.1595629
Filename
1595629
Link To Document