3621022

Design Methodologies and CAD Tool Flows for Networks on Chips

S. Murali

Stanford University, smurali@stanford.edu

2005

6/27/1905 12:00:00 AM

1

1

"Design methodology","Design automation","Network-on-a-chip","Traffic control","Process design","Telecommunication traffic","Algorithm design and analysis","Routing","Very large scale integration","Bandwidth"

ieee

System-on-Chip, 2005. Proceedings. 2005 International Symposium on

0-7803-9294-9

conf

10.1109/ISSOC.2005.1595629

1595629