Numerical Analysis of DGMOSFET 1/f Noise Under Different Bias Conditions

Author

M. Videnovic-Misic;M.M. Jevtic

Author_Institution

Student Member IEEE, Department of Electronics, Faculty of Technical Sciences, University of Novi Sad, Trg Dositeja, Obradovica 6, 21000 Novi Sad, Serbia &

Volume

2

fYear

2005

fDate

6/27/1905 12:00:00 AM

Firstpage

1232

Lastpage

1235

Abstract

In this paper I_D-V_DS characteristics and numerical analysis of 1/f noise for DGMOSFET and its transistors are presented. A model of DGMOSFET noise analysis based on small signal noise equivalent circuits is proposed. Using this model we have calculated the weighting factors that describe participation of source and drain transistor noises in total noise. It is found that DGMOSFET 1/f noise is lower than noise of the first (source) and second (drain) transistors if the first transistor is in linear or partially non-linear regions. Moreover, resultant DGMOSFET noise is lower than source transistor noise under all bias conditions. If source and drain transistors are in non-linear and/or saturation regimes, the source transistor dominantly influences DGMOSFET noise

Keywords

"Numerical analysis","Low-frequency noise","Circuit noise","Oscillators","Phase noise","Equivalent circuits","MOSFET circuits","Radio frequency","Voltage","Signal analysis"

Publisher

ieee

Conference_Titel

Computer as a Tool, 2005. EUROCON 2005.The International Conference on

Print_ISBN

1-4244-0049-X

Type

conf

DOI

10.1109/EURCON.2005.1630178

Filename

1630178