Design and verification methodology for reconfigurable designs in atmel FPSLIC

Partial dynamic reconfiguration enables designs with increased functional density and lower power consumption, but on the other hand it increases the complexity of the design process. This paper describes a methodology and design flow for designs with dynamic reconfiguration in the DSP and control domain. The described design flow starts with a description in Matlab/Simulink that is converted to Handel-C and then compiled through VHDL to EDIF, and finally to FPGA configuration. The methodology and design flow are demonstrated on implementation examples with simple floating point IP cores targeting the Atmel AT94K FPSLIC device