Title :
Test Scheduling for SOC under Power Constraints
Author_Institution :
Fac. of Inf. Technol., Brno Univ. of Technol. Bozetechova
fDate :
6/28/1905 12:00:00 AM
Abstract :
This paper deals with test scheduling under power constraints. An approach based on genetic algorithm operating on test application conflict graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC´02 SOC benchmark suite are presented in the paper together with the perspectives for the future research
Keywords :
"System testing","Circuit testing","Power dissipation","Power system modeling","Logic testing","Genetic algorithms","Electronic equipment testing","Information technology","Paper technology","Resource management"
Conference_Titel :
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Print_ISBN :
1-4244-0185-2
DOI :
10.1109/DDECS.2006.1649583
