• DocumentCode
    3622201
  • Title

    Detecting masquerading attack in software and in hardware

  • Author

    V. Pejovic;S. Bojanic;C. Carreras;O. Nieto-Taladriz

  • Author_Institution
    Dept. de Ingenieria Electron., Univ. Politecnica de Madrid, Spain
  • fYear
    2006
  • fDate
    6/28/1905 12:00:00 AM
  • Firstpage
    836
  • Lastpage
    838
  • Abstract
    Masquerading attack is one of the most dangerous system intrusions. It is very hard to detect this attack, especially in real time for actual network speed rates. In this work the software and hardware approaches for the detection of attacker are analyzed. It is observed that the software solution could not easily reach the necessary rates and the hardware solution is applied in order to achieve the required throughput. Careful analysis of the bioinformatics pattern matching algorithm that is used indicates that exploiting parallelization could improve the performances. Implementing the modified bioinformatics algorithm in the FPGA can increase for several orders the speed in detection process and achieve the necessary results
  • Keywords
    "Hardware","Bioinformatics","Throughput","Pattern analysis","Performance analysis","Algorithm design and analysis","Pattern matching","Field programmable gate arrays","Software performance"
  • Publisher
    ieee
  • Conference_Titel
    Electrotechnical Conference, 2006. MELECON 2006. IEEE Mediterranean
  • ISSN
    2158-8473
  • Print_ISBN
    1-4244-0087-2
  • Electronic_ISBN
    2158-8481
  • Type

    conf

  • DOI
    10.1109/MELCON.2006.1653228
  • Filename
    1653228