DocumentCode
3622973
Title
Is there any future for deterministic self-test of embedded RAMs?
Author
A. Krasniewski;K. Gaj
Author_Institution
Inst. of Telecommun., Warsaw Univ. of Technol., Poland
fYear
1993
fDate
6/15/1905 12:00:00 AM
Firstpage
159
Lastpage
168
Abstract
The authors demonstrate that RAM BIST techniques based on deterministic test procedures are very inefficient in detection of non-target faults, i.e., faults not included in fault models used for test development. Estimates of the defect coverage indicate that deterministic RAM BIST schemes are unlikely to meet future test quality requirements. The authors also show that, contrary to common belief, self-test schemes based on random patterns have a potential to provide, a very high quality of testing within acceptable time limits for megabit embedded memories.
Keywords
"Built-in self-test","Circuit faults","Read-write memory","Automatic testing","Circuit testing","Random access memory","Fault detection","Very large scale integration","Digital signal processing chips","Failure analysis"
Publisher
ieee
Conference_Titel
European Test Conference, 1993. Proceedings of ETC 93., Third
Print_ISBN
0-8186-3360-3
Type
conf
DOI
10.1109/ETC.1993.246521
Filename
246521
Link To Document