Transformation-based register optimization in high-level synthesis

A novel approach to temporary register minimization that exploits the power of behavioral transformations is proposed. Behavioral transformations allow one to reduce the register requirements below the inherent lower bound imposed by the structure of the input flow graph. Specifically, the transformations minimize the lifetimes of registers in a scheduled flow graph. The transformations are applied across clock cycle boundaries with peak register use. Preliminary results for the benchmark examples show a significant reduction in the number of registers.