DocumentCode
3623112
Title
ALMP: a shifting memory architecture for loop pipelining
Author
H.F. Ugurdag;C.A. Papachristou
Author_Institution
Dept. of Electr. Eng. & Appl. Phys., Case Western Reserve Univ., Cleveland, OH, USA
fYear
1992
fDate
6/14/1905 12:00:00 AM
Firstpage
564
Lastpage
568
Abstract
A multiprocessor architecture called ALMP, which specifically suits loop pipelining, is proposed. The processors in ALMP work like machines in an assembly line in a plant. An assembly line scheduling method (ALMap) has also been developed. ALMP enables processors to communicate with each other through memory modules that shift from processor to processor as if they are on a conveyor belt. The scheduling method is briefly described, and architectural issues are examined.
Keywords
"Memory architecture","Pipeline processing","Assembly","Job shop scheduling","Processor scheduling","Belts","Hardware","Delay","Multiprocessor interconnection networks","Physics"
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1992. ICCD ´92. Proceedings, IEEE 1992 International Conference on
Print_ISBN
0-8186-3110-4
Type
conf
DOI
10.1109/ICCD.1992.276224
Filename
276224
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