High-level synthesis of self-recovering microarchitectures

A methodology for the computer aided synthesis of microarchitectures that can recover from transient faults is presented. The synthesis is formulated as a two-step procedure of checkpoint insertion followed by duplication. The checkpoint insertion technique minimizes the voting overhead subject to input constraints on maximum allowable recovery time and the maximum number of retries. Additionally checkpoint insertion is interspersed with the scheduling decisions of a novel edge-based scheduler. Self-recovering microarchitectures which perform optimally but require less than proportional increase in hardware are generated by exploiting cost minimizing transformations.