Rapid prototyping of fault tolerant VLSI systems

We relate fault-tolerance constraints to chip area and present a methodology for rapidly compiling an algorithmic description into area-efficient fault-tolerant VLSI ICs. Whereas detection and recovery from environment induced transient faults is accomplished by checkpointing and rollback, uninterrupted operation for the lifetime of a mission is ensured by injecting redundancy. Towards validating this methodology, we synthesized fault tolerant implementations of a 16-point FIR filter starting from an algorithmic description. These fault-tolerant designs were then critically appraised.