Memory-I/O tradeoff and VLSI implementation of lapped transforms for image processing

The authors describe a new system architecture for real-time two-dimensional image block processing by separable lapped transforms (LTs). The main advantage of this image block 2-D LT is the reduction of the transposition memory size and its on-chip integration. The tradeoff between input/output (I/O) throughput and on-chip memory size is discussed. The design of the transposition memory and its VLSI complexity performacne in terms of areas and speed are presented.