Fine-grained concurrency in test scheduling for partial-intrusion BIST

Partial-intrusion BIST reduces area overhead and increases chip performance by reducing the number of test registers, but it requires a test schedule definition. The scheduling of the tests impacts directly the test application time. This paper presents a novel model of the test plan scheduling problem for partial-intrusion BIST circuits. Test application time is reduced by performing scheduling to allow the execution of test plans in a pipelined fashion. Test scheduling conflicts are avoided by exploiting the parallelism which is revealed by a flexible test representation; consequently, test concurrency is increased. Computational efficiency is gained by performing incremental, subtractive heuristic test scheduling decisions. The effects of each test decision are rigorously propagated, limiting the test scheduling possibilities to only those which lead to a feasible scheduling solution. Experimental results show that high levels of test concurrency are achieved in a computationally efficient manner by limiting the state of the scheduling search space using conflict probability estimation and rigorous pruning of infeasible test options.