Integrating binding constraints in the synthesis of area-efficient self-recovering microarchitectures

Fault-tolerance increases hardware reliability of a VLSI design but it also has the disadvantage of increasing chip area. This area overhead can however be minimized by consideration of fault-tolerance during the high-level synthesis stage of design. We introduce an intertwined scheduling and binding algorithm for self-recovering fault-tolerant designs. Two copies in a self-recovering design have to be performed by disjoint sets of hardware to maintain fault-tolerance under a single fault assumption. The proposed algorithm is the first that satisfies the hardware disjointness condition which is necessary for fault-tolerant design. Area efficient self-recovering microarchitectures are achieved through novel binding techniques which influence scheduling decisions. Various synthesis benchmarks are used to illustrate the effectiveness of this approach.