Designing mixed-mode test pattern generators for minimum-overhead self-testing VLSI circuits

A simple technique for designing self-testable VLSI circuits, characterized by low silicon area overhead and maximum testing speed, is proposed. An original feature of this built-in self-test design technique is a procedure for synthesis of test pattern generators. Its objective is to design mixed-mode generators of minimal complexity that maximize the fault-sensitizing capabilities of test sequences produced within the allowable test running time. The approach does not require that any internal register of the original circuit be modified, and the built-in test control logic is extremely simple. Applying test patterns on consecutive clock cycles with the normal-operation clock frequency leads to substantial enhancement of dynamic fault-detection capabilities.