An implementation of hash based ATM router chip

Routing in the ATM environment requires fast handling of large size routing tables, forcing high speed network nodes to implement appropriate hardware support for routing. Traditional solution for this problem is to use associative memories; however, for the ATM router this solution may require an excessively large chip area and power consumption. This paper presents an original architecture of the hash-based hardware accelerator which makes use of standard RAM. Results of analytical simulation, and implementation analysis given in the paper indicate the price/performance ratio which is up to an order of magnitude better compared to some of the existing solutions.