Timing verification of NMOS logic circuits

A set of procedures that can be used to check NMOS logic circuits for timing errors is presented. The procedures find the path which could cause timing errors, and calculate the delays along those paths. The determination of these delays can be performed either before layout, using estimated values for the interconnected capacitance, or after layout, when the exact values are available. The advantage of using path delay computation for timing verification, as opposed to detailed timing simulation, is also discussed.