A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM

An architecture for enabling self-authenticating chips uses 4 Kb electrically programmable fuses (eFUSE) to store bit strings representing encrypted intrinsic fingerprints obtained by offset-superimposing six out of one thousand 4 Kb domains randomly chosen in 4 Mb embedded DRAM. Authentication is accomplished by regenerating various encrypted intrinsic fingerprints, which are then compared with the bit strings in the eFUSE. Monte Carlo simulations demonstrate that, targeting an average of 32 retention fails per domain, the strings are unique and authentication is statistically guaranteed without bit correction even when unstable bits are introduced. The preliminary results are confirmed in > 50 parts containing 4 Mb memory implemented in 22-nm SOI hardware under the target voltage ±10% conditions. The analytical model predicts > 10 ²⁰ years to crack the encryption by brute force, while satisfying > 99.9999% successful authentication for one million parts.