GEN03-5: Construction of Memory Circuits Using Unreliable Components Based on Low-Density Parity-Check Codes

In this paper, we analyze storage circuits constructed from unreliable memory components. We propose a memory construction, using low-density parity-check codes, based on a construction originally made by Taylor. The storage circuit consists of unreliable memory cells along with a correcting circuit. The correcting circuit is also constructed from unreliable logic gates along with a small number of perfect gates. The modified construction enables the memory device to perform better than the original construction. We present numerical results supporting our claims.