Filter Hardware Cost Reduction by Means of Error Feedback

The article presents an uncommon application of the error feedback-improved IIR filter. A simple method to reduce the hardware cost (silicon area) of the biquadratic section implementation by means of error feedback (EF) is described. The optimization method utilizes the fact that the filter with an EF is more resistant to roundoff noise than a filter without it. An iterative method is used to reduce the occupied silicon area. First the standard IIR filter is designed with the requested quantization properties. Then the EF-improved biquadratic section is designed to attain the same roundoff noise properties. The occupied silicon areas of both solutions are compared then. Although implementation of EF results in more arithmetic components and more complex filter control, the resulting structure attaining the same quantization noise is smaller under defined circumstances (filter with poles close to the unit circle). Results show it is possible to spare up to 22% of the occupied silicon area. Our findings are valid for FPGA as well as ASIC implementation of the IIR filters. Our method has an advantage in using a standard and already verified filtering IP core which results in design time reduction.