Simulation of Digital Clock and Data Recovery of Strongly Disturbed Signals

The paper describes a simulation model of a software and hardware recovery circuit. Performance of both models is compared and drawbacks of software recovery are discussed. To model different link conditions, signal source and data path models were created (to model jitter and noise of received signal). All simulations were performed in the Mentor Graphic´s SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The software recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design.