Digital Controller for High-Frequency Rectifiers with Power Factor Correction Suitable for On-Chip Implementation

This paper describes a digital controller for high-frequency single-phase power factor correction rectifiers (PFC) that is suitable for on-chip implementation. To achieve high switching frequency, fast dynamic response, and implementation with a small number of logic gates, the designs of basic functional blocks are optimized. In the outer voltage loop a windowed based analog-to-digital converter (ADC) with adjustable quantization steps is used, to achieve fast dynamic response. The complexity of the current loop realization is significantly reduced through the utilization of a floating reference created by a Sigma-Delta modulator and another windowed based ADC. In addition, a segmented ring-oscillator based digital pulse-width modulator (DPWM) is used to eliminate the need for a high frequency external clock and reduce the overall size of the system. The effectiveness of this digital architecture is demonstrated on a 200 kHz, 300 W boost-based PFC experimental prototype.