Title :
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR
Author :
Brian S. Leibowitz;Jade Kizer;Haechang Lee;Fred Chen;Andrew Ho;Metha Jeeradit;Akash Bansal;Trey Greer;Simon Li;Ramin Farjad-Rad;William Stonecypher;Yohan Frans;Barry Daly;Fred Heaton;Bruno W. Garlepp;Carl W. Werner;Nhat Nguyen;Vladimir Stojanovic;Jared L.
Author_Institution :
Rambus, Los Altos, CA
Abstract :
A 7.5Gb/s receiver has a 3-level DFE architecture to satisfy feedback timing requirements for 10 post-cursor taps. The receiver includes a second-order CDR with partial-response transition data filtering as well as a spectrally gated adaptation engine to prevent equalization updates during poor data patterns. The receiver consumes 136mW in a 90nm CMOS process
Keywords :
"Decision feedback equalizers","Timing","Hardware","Intersymbol interference","Delay","Testing","Backplanes","Logic","Multiplexing","Clocks"
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Print_ISBN :
1-4244-0852-0
Electronic_ISBN :
2376-8606
DOI :
10.1109/ISSCC.2007.373377
