Title :
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes
Author :
Fabrice Monteiro;Stanislaw J. Piestrak;Houssein Jaber;Abbas Dandache
Author_Institution :
University of Metz, France
fDate :
7/1/2007 12:00:00 AM
Abstract :
The problem of designing a fault-secure interface between a fault-tolerant RAM memory system and a transmission channel, both protected against errors using cyclic linear error detecting and/or correcting codes is considered. The main idea relies on using the RAM check bits to control the correct operation of the parallel cyclic code encoder, so that the whole interface has no single point of failure.
Keywords :
"Fault tolerant systems","Read-write memory","Circuit faults","Random access memory","Protection","Error correction codes","Error correction","Fault detection","Electrical fault detection","Semiconductor device noise"
Conference_Titel :
On-Line Testing Symposium, 2007. IOLTS 07. 13th IEEE International
Print_ISBN :
0-7695-2918-6
DOI :
10.1109/IOLTS.2007.32
