Development of MPW Service for Academies Based on ITE Proprietary CMOS Process

A MPW service has been arranged in the ITE in order to offer facility to academies for prototyping of CMOS ICs. This service is based on the proprietary CMOS process. The technology has been characterized via electrical measurements of dedicated test structures. The characteristics have been implemented in the form of design kit. Cadence reg design system has been chosen as a target tool for ICs design because of its popularity in European academies due to availability via EUROPRACTICE program. A number of functionalities have been implemented in the design kit. Namely, layout verification procedures (DRC, extraction, LVS) for Diva (TM) and Assura (TM) applications, automated generation of auxiliary technological layers (using Assura), layout import / export (GDSII, CIF formats) and corner analysis. Hence, a complete tool for ASICs design at the universities has been established.