Static Power Reduction in Nano CMOS Circuits Through an Adequate Circuit Synthesis

This paper addresses the power reduction issues in nano CMOS circuits, and focuses on the static-power and power-efficient circuit synthesis. It shows that the circuit synthesis approaches applied in today´s commercial EDA-tools are not power-efficient in most cases, and experimentally demonstrates a high power-reduction potential of an adequate circuit synthesis. It also shows that our novel information-driven approach to circuit synthesis is able to robustly construct low-power circuits for the contemporary and future CMOS circuits.