Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA´s

Modern FPLD devices have a very complex structure. They combine PLA-like structures as well as FPGA´s and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLD´s to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation is presented. We pinpoint the sources of additional optimization of the functional decomposition and relate them to the state encoding conditions. The method is based on a reduction of a state assignment problem to a graph coloring problem. To this end, the so called multi-graph of incompatibility of memory T-words is applied. As a result, a new design technique for implementation of sequential circuits using embedded memory blocks of FPGA´s has been developed. Preliminary experimental results are extremely encouraging.