Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor

This paper proposes a new approach for the optimization process of the interval addition and multiplication floating point units. For the interval addition/subtraction, an adder exploiting the parallelism of the double path adder structure is used. The two floating point additions needed are performed simultaneously on different data paths. Therefore, the performance of the proposed adder can be the same as that of two individual floating point adders, but with a much reduced cost overhead. Regarding the interval multiplication, a multiplier architecture was designed, in order to be suitable for pipelined structures. It consists of a floating point multiplier which computes two results for the same operation (rounded differently), and of two floating point comparators. In terms of performance, the proposed multiplier unit presents half of the performance of a conventional floating point multiplier. This is not a drawback, if we consider the fact that interval multiplication requires four floating point operations and six comparisons. This paper shows that interval arithmetic can be efficiently implemented in terms of performance and cost.