• DocumentCode
    3625781
  • Title

    Open Defects Caused by Scratches and Yield Modelling in Deep Sub-Micron Integrated Circuit

  • Author

    Wlodzimierz Jonca

  • Author_Institution
    Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland. Email: wjonca@gmail.com
  • fYear
    2007
  • fDate
    4/1/2007 12:00:00 AM
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper tries to find out whether commonly used spot defect fault model is still viable for deep sub-micron (DSM) integrated circuits´ test and yield model. It is believed that for DSM products spot defects may be no longer major source of yield loss. Results from number of computer experiments are presented and discussed.
  • Keywords
    "Integrated circuit modeling","Integrated circuit yield","Circuit testing","Microelectronics","Time to market","Predictive models","Integrated circuit technology","Paper technology","Circuit faults","Integrated circuit testing"
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS ´07. IEEE
  • Print_ISBN
    1-4244-1161-0
  • Type

    conf

  • DOI
    10.1109/DDECS.2007.4295314
  • Filename
    4295314
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3625781