• DocumentCode
    3626056
  • Title

    Fault Tolerant Memories Based on Expander Graphs

  • Author

    Shashi Kiran Chilappagari;Bane Vasic

  • Author_Institution
    Dept. of Electrical and Computer Eng., University of Arizona, Tucson, AZ 85721, USA. Email: shashic@ece.arizona.edu
  • fYear
    2007
  • Firstpage
    126
  • Lastpage
    131
  • Abstract
    In this paper we consider memories built from components subject to transient faults. We propose a fault-tolerant memory architecture based on LDPC codes and show the existence of memories which can tolerate constant fraction of failures in all the components. Our proof relies on the expansion property of the underlying Tanner graph of the code. We illustrate our results with specific numerical examples.
  • Keywords
    "Fault tolerance","Graph theory","Circuit faults","Parity check codes","Decoding","Redundancy","Memory architecture","Error correction codes","Lakes","Mathematics"
  • Publisher
    ieee
  • Conference_Titel
    Information Theory Workshop, 2007. ITW ´07. IEEE
  • Print_ISBN
    1-4244-1563-2
  • Type

    conf

  • DOI
    10.1109/ITW.2007.4313061
  • Filename
    4313061
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3626056