Power Reduction Technique for Successive-Approximation Analog-to-Digital Converters

This paper addresses the problem of reducing power consumption in successive approximation ADC architecture as a building block of power-aware electronic devices. Two binary search control algorithms, intended to decrease the total ADC´s consumed energy during the conversion cycle are proposed in this paper. Both algorithms take advantage of sensor input signal properties and dynamically reduce the number of conversion steps in order to save energy. Metrics for evaluating energy efficiency of the conversion process, called energy reduction factor, F_er is involved. Simulation results show that energy saving per conversion cycle of up to 25 % can be obtained.