Towards an Improved Integrated Coherence and Speculation Protocol

The first concern of this paper is to explore the possibilities for performance and complexity improvements in speculative chip multiprocessors. To this end, it analyses integrated speculation and coherence protocols in current chip multiprocessors and identifies four areas (hardware overhead, software overhead, bursty traffic on thread commit, and replacement policy) where some improvements can be made. Conclusions of this analysis have inspired some decisions in a new proposal which is briefly sketched in the rest of the paper.