Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

The silicon-on-nothing (SON) technology promises improved short-channel performance for ultra-scaled CMOS, without the added cost of the UTB SOI wafers (M. Jurczak et al., 200). The vertical fully- depleted SON concept (VFD SONFET) demonstrates the vertical SON structure, using the active transistor region grown on the sidewall of the Si/SiGe/Si stack with subsequent highly-selective SiGe removal (P.E. Thompson et al., 2005). As well as the improved SCE, the standard bulk region is eliminated in the VFD SONFET, making it a three-terminal device with well-controlled dimensions by the thickness of the grown layers. The absence of the transistor bulk is a unique property of the VFD SONFET, not present in either bulk or SOI CMOS, and the compact capacitance model is developed to describe the two-dimensional nature of this fully-depleted MOS structure. The calculation of the threshold voltage (V,h) using the compact model is presented in this paper.