Power-Limited Design

Technology scaling has entered a new era, where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate the choice of technology, and architecture, and dictate the use of implementation techniques that trade off performance for power savings. This paper examines the technology options in the power-limited scaling regime, and reviews sensitivity-based analysis that can be used for the optimal selection of power-performance tradeoffs, to achieve the best performance under the power constraints. These tradeoffs are examined on the techniques for power minimization at the technology, circuit, logic, and architecture levels.