Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform

This paper deals with the implementation issues of building Virtual Testing Environment (VTE) for performance extraction of A/D converters. Here, the term "virtual" implies to the fact that the ADC testing is done yet in the circuit design on a base of an ADC model capable to capture the ADC error sources occurring in the integrated circuit structure. The first part of the contribution concerns significant properties of two proposed VTE algorithm implementations, the first one employing Verilog-A behavioral module and the second which is created in Maple environment with built-in libraries for circuit analysis. The performance of both VTE implementations is evaluated at system-level and by simulation of residual non-linearity with an ideal ADC model. Throughout the article, a stress is given to the building procedure which was necessary to create VTE capable to work both on Verilog-A and Maple platform.