Title :
Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation
Author :
J. Brenkus;V. Stopjakova;J. Mihalov
Author_Institution :
Department of Microelectronics, Slovak University of Technology, Ilkovicova 3, 812 19 Bratislava, Slovak Republic, juraj.brenkus@stuba.sk
Abstract :
An experimental analog design for parametric test methods efficiency evaluation is presented. The circuit is implemented in a standard 0.35?m CMOS process by AMS. The circuit under test (CUT) is a two-stage operational amplifier with implemented addressable faults. The control of the overall circuit is ensured by a 7-bit shift register. For higher loading capability a buffer is connected to the output. To preserve the possibility of voltage ramping, the CUT has a separated supply rail. The CUT can be also connected to a feedback network integrated on the chip, and thus, turned into an oscillator.
Keywords :
"Circuit testing","Analog circuits","CMOS process","Operational amplifiers","Circuit faults","Shift registers","Voltage","Rails","Feedback","Oscillators"
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Print_ISBN :
978-1-4244-2276-0
DOI :
10.1109/DDECS.2008.4538805
