Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation

An experimental analog design for parametric test methods efficiency evaluation is presented. The circuit is implemented in a standard 0.35?m CMOS process by AMS. The circuit under test (CUT) is a two-stage operational amplifier with implemented addressable faults. The control of the overall circuit is ensured by a 7-bit shift register. For higher loading capability a buffer is connected to the output. To preserve the possibility of voltage ramping, the CUT has a separated supply rail. The CUT can be also connected to a feedback network integrated on the chip, and thus, turned into an oscillator.