Innovative lateral field plates by gate fingers on STI regions in deep submicron CMOS

This paper demonstrates experimentally a novel design of medium voltage MOSFETs in 65nm baseline low-voltage CMOS with state-of-the-art Ron performance. The HV capability is achieved through layout innovation independently from the available process. We demonstrate that gate fingers on STI regions interleaving the drain extension can be used as field plates enhancing the reverse voltage capability of EDMOS transistors. In this layout definition of lateral field plates, the effective field plate capacitance is determined by the lateral distance between the gate finger and the drain extension. Such an implementation allows process-less field plate capacitors graded along the drain extension enabling more flexible electrical field shaping as compared to classical field plates in the dielectric stack. A substantial (~1.65x) improvement of Ron vs. BVds is demonstrated with such gate finger field plates.