Title :
A dual-core programmable decoder for LDPC convolutional codes
Author :
Marcos B.S. Tavares;Emil Matus;Steffen Kunze;Gerhard P. Fettweis
Author_Institution :
Technische Universit?t Dresden, D-01062, Germany
fDate :
5/1/2008 12:00:00 AM
Abstract :
We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tail-biting LDPC convolutional codes. This architecture has a very good scalability and is fully programmable so that it can be applied to several communications and data storage scenarios. The synthesis results show relatively small area consumption for very high decoding speeds.
Keywords :
"Decoding","Parity check codes","Convolutional codes","Computer architecture","Throughput","Interleaved codes","Memory architecture","Scalability","Tail","Equations"
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
2158-1525
DOI :
10.1109/ISCAS.2008.4541472
