• DocumentCode
    3628051
  • Title

    Limits to a correct operation in RTD-based ternary inverters

  • Author

    Juan Nunez;Jose M. Quintana;Maria J. Avedillo

  • Author_Institution
    Instituto de Microelectr?nica de Sevilla, Centro Nacional de Microelectr?nica, Consejo Superior de Investigaciones, Cient?ficas (CSIC) and Universidad de Sevilla, Edificio CICA, Avda. Reina Mercedes s/n, 41012, SPAIN
  • fYear
    2008
  • fDate
    5/1/2008 12:00:00 AM
  • Firstpage
    604
  • Lastpage
    607
  • Abstract
    Multiple-valued logic (MVL) circuits are one of the most attractive applications of the monostable-to-multistable transition logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.
  • Keywords
    "Inverters","Logic circuits","Voltage","Piecewise linear techniques","Circuit topology","Resonant tunneling devices","Temperature","III-V semiconductor materials","HEMTs","Nanoscale devices"
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4244-1683-7
  • Electronic_ISBN
    2158-1525
  • Type

    conf

  • DOI
    10.1109/ISCAS.2008.4541490
  • Filename
    4541490
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3628051