Error significance map for bit-plane FIR filtering array

Some applications require correct computation, while many others do not. Large domain where perfect functional performance is not always required is in multimedia and DSP systems. Relaxing the requirement of 100% correctness for devices and interconnections may dramatically reduce costs of manufacturing, verification, and testing. The goal of this paper is development of error significance map for bit-plane FIR filtering array. The map marks the part of the array that must be error-free in order to enable computing on the bit-plane array with acceptable results. In other words the array cells, out of the marked area, could produce errors, but without significant influence on the marked high order bits of the resulting word. The bit-plane array operates on a bit level and assumes accumulation throughout the array with sum and carry propagation. It means that derivation of the error significance map is not a trivial for design automation. In this paper we propose a rigorous mathematical path based on transitive closure that generates error significance map for the bit-plane array.